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CORE-ET currently hosts the CORE-ET Agentic Silicon Platform (ETASP), which organizes reusable hardware IP for translation, verification, documentation, and integration by agent-assisted development workflows. The main branch is translating the original CORE-ET modules into documented lowRISC-style SystemVerilog with technology abstractions and Verilator-based testing, while the historical RTL and microarchitecture material remain on the erbium branch. Readers should choose the main branch to study the current IP-workflow experiment and the erbium branch when they need the original manycore/MRAM-era implementation.
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Category: IP ComponentsStatus: Editorial · ActiveBest for: Researcher
At a glance
- Current identity: CORE-ET Agentic Silicon Platform (ETASP), an Ainekko project
- Main-branch work: documented, lowRISC-style SystemVerilog translations of original CORE-ET modules
- Verification: Verilator unit tests and side-by-side RTL co-simulation against the original source tree
- Technology abstraction: generic simulation plus iCE40 and Xilinx FPGA implementations; ASIC support remains future work
- Historical boundary: original CORE-ET RTL and microarchitecture documentation remain on the erbium branch
Further resources
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SystemVerilogrepository language (GitHub)
Categories
IP ComponentsSoC & Subsystem
Tags
OpenHWRISC-VIPSoCSilicon PlatformAgenticIP CatalogSystemVerilog
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Contribution ActivityLow Activity
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Data as of Oct 12, 2026
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