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CV32E20 Design Verification

ActiveOpenHW Explorer editorial assessment

cv32e20-dv is the core-specific design-verification environment for CV32E20/CVE2. It adds the SystemVerilog environment, board-support package, testbench, and C or assembly test programs that are specific to this small two-stage core, while reusing common agents and infrastructure from core-v-verif. Engineers working on CVE2 should use this repository for target-specific tests and use the shared CORE-V-VERIF guide for initial tool and environment setup.

Reviewed profileOfficial sourcesVerified 2026-07-165 sourcesPrimary source
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Category: VerificationStatus: Editorial · ActiveBest for: Engineer
Start with GitHub

At a glance

  • Target: core-specific design-verification environment for CV32E20/CVE2
  • Sources: CV32E20-specific SystemVerilog plus C and assembly test programs
  • Structure: BSP, UVM environment, simulation area, testbench, and test cases
  • Shared components: agents such as the OBI agent are consumed from the vendored core-v-verif library
  • Setup path: common tool and environment preparation follows the CORE-V-VERIF Quick Start Guide

Further resources

CVE2 repositoryCV32E20 RTL under verificationCVE2 User Manualofficial core documentationCORE-V-VERIF Quick Start Guidesetup guidance referenced by the repositoryCORE-V verification environmentsource of shared verification components
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Categories

Verification

Tags

OpenHWRISC-VVerificationUVM TestbenchDirected TestsCore DVAssemblyCVE2DV

Suitable For

EngineerContributor

Verification Type

UVM Testbench

Contribution ActivityLow Activity

12

Contributors

6

Open Issues

2

Recent Commits (4 weeks)

7

Open PRs

Data as of Oct 12, 2026

Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.

Related Projects

CVE2 (CV32E20)

CVE2 is OpenHW's low-complexity embedded-core family, currently represented by the two-stage CV32E20 processor. The 32-bit, in-order design supports RV32I or RV32E, compressed instructions, and configurable multiplication/division. It suits control-oriented systems where area and energy matter more than peak performance. Students can use it to understand a small modern pipeline, while engineers should pair the RTL with cv32e20-dv and the shared core-v-verif infrastructure for verification work.

CORE-V Verification

core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.

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