cv32e20-dv is the core-specific design-verification environment for CV32E20/CVE2. It adds the SystemVerilog environment, board-support package, testbench, and C or assembly test programs that are specific to this small two-stage core, while reusing common agents and infrastructure from core-v-verif. Engineers working on CVE2 should use this repository for target-specific tests and use the shared CORE-V-VERIF guide for initial tool and environment setup.
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CVE2 is OpenHW's low-complexity embedded-core family, currently represented by the two-stage CV32E20 processor. The 32-bit, in-order design supports RV32I or RV32E, compressed instructions, and configurable multiplication/division. It suits control-oriented systems where area and energy matter more than peak performance. Students can use it to understand a small modern pipeline, while engineers should pair the RTL with cv32e20-dv and the shared core-v-verif infrastructure for verification work.
core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.