Back to ProjectsStart with GitHub
cv32e40s-dv is the core-specific verification repository for the security-oriented CV32E40S processor. It organizes software test compilation, UVM infrastructure, simulation, top-level testbench code, test cases, and formal-verification work into separate areas. Engineers changing CV32E40S RTL can use it to locate the relevant dynamic or formal flow. The default branch received a Sail interrupt-generator and CLINT integration update in July 2026; this establishes recent maintenance, not complete verification coverage or a particular release maturity.
Start here
Category: VerificationStatus: Editorial · ActiveBest for: Engineer
At a glance
- Target: design-verification environment for the CV32E40S core
- BSP: compiles, assembles, and links test programs for the core and UVM environment
- UVM structure: environment class and supporting infrastructure live under env
- Flow separation: simulation, testbench, test cases, and formal work have dedicated directories
- Maintenance evidence: a July 27, 2026 default-branch merge integrates the Sail interrupt generator and CLINT mtime/mtimecmp support; activity does not establish verification completeness
Further resources
1stars
3forks
Assemblyrepository language (GitHub)
Categories
Verification
Tags
OpenHWRISC-VVerificationUVM TestbenchFormal VerificationSecurity DVCore DVAssemblySecurityDV
Suitable For
Engineer
Verification Type
UVM TestbenchFormal Verification
Contribution ActivityLow Activity
15
Contributors
1
Open Issues
0
Recent Commits (4 weeks)
0
Open PRs
Data as of Oct 12, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CV32E40S
CV32E40S is a compact four-stage, in-order 32-bit RISC-V core designed for security-oriented embedded systems. Building on the CV32E40P lineage, it adds Machine and User privilege modes, enhanced physical memory protection, anti-tampering mechanisms, and the Xsecure extension set. It is a relevant choice when evaluating protection-focused MCU designs; it should not be confused with the lockstep and fault-tolerance work in CVA6-Safe.
CORE-V Verification
core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.