CVA6 Platform is an older multicore CVA6 and CV-MESH system assembled on top of OpenPiton for software testing and regression. It provides a pre-built Genesys 2 bitstream and Fedora image as well as a full path for rebuilding FPGA hardware, OpenSBI firmware, U-Boot, and Linux. The repository is useful when reproducing this specific OpenPiton-based platform, but its inactive maintenance state makes the current CVA6 repository and SDKs better starting points for new single-core or actively supported work.
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CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.
CV-MESH is an early-stage OpenHW repository for cache-coherence and interconnect components derived from the OpenPiton context. Its public tree contains bridges, L1.5 and L2 cache logic, and network-on-chip blocks, and related OpenHW platforms use CV-MESH in multicore integration work. Public top-level documentation is still missing, so the repository is suitable mainly for experienced engineers tracing existing RTL; topology, supported scale, protocol details, and maturity cannot yet be assessed from a stable public specification.
CORE-V Polara APU is a multicore vector-processing research platform that combines ideas and code from Ara with the OpenPiton manycore infrastructure. Its documented configuration connects four RISC-V vector cores and includes low-precision operations relevant to DNN inference. The repository is aimed at researchers evaluating vector and multicore systems; reproducing its flows requires a vector-capable RISC-V LLVM toolchain and supported commercial simulators.