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OBI (OpenBus Interface)

MatureOpenHW Explorer editorial assessment

OBI is the specification repository for the OpenBus Interface, a lightweight on-chip protocol used by several CORE-V embedded processors for instruction and data-memory access. The repository publishes versioned specification documents rather than RTL, while processor manuals and verification projects provide concrete master, slave, and agent implementations. Use it when integrating a CORE-V memory interface or building compatible interconnect and verification components.

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Category: IP ComponentsStatus: Editorial · MatureBest for: Engineer
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At a glance

  • Integration boundary: select the OBI version implemented by the target core and peripheral; the newest specification does not automatically describe every existing core interface
  • Artifact type: versioned protocol specification rather than RTL
  • Published documents: OBI v1.0 through OBI v1.6.0 are present in the repository
  • CORE-V usage: instruction and data-memory interfaces in processors including CV32E40P and CV32E20
  • Implementation boundary: concrete protocol logic and verification agents live in consuming core and DV repositories

Further resources

OBI v1.6.0 specificationlatest versioned PDF currently present in the repositoryCV32E40P User Manualcore interfaces using OBICV32E20 design verificationverification environment that consumes an OBI agent from core-v-verifCORE-V verification environmentsource of shared bus-agent infrastructure
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Categories

IP ComponentsDocumentation

Tags

OpenHWRISC-VIPDocumentationBus InterfaceSpecificationOBI

Suitable For

Engineer

Contribution ActivityLow Activity

2

Contributors

0

Open Issues

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Recent Commits (4 weeks)

0

Open PRs

Data as of Oct 12, 2026

Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.

Related Projects

CV32E40P

CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.

CVE2 (CV32E20)

CVE2 is OpenHW's low-complexity embedded-core family, currently represented by the two-stage CV32E20 processor. The 32-bit, in-order design supports RV32I or RV32E, compressed instructions, and configurable multiplication/division. It suits control-oriented systems where area and energy matter more than peak performance. Students can use it to understand a small modern pipeline, while engineers should pair the RTL with cv32e20-dv and the shared core-v-verif infrastructure for verification work.

CV32E20 Design Verification

cv32e20-dv is the core-specific design-verification environment for CV32E20/CVE2. It adds the SystemVerilog environment, board-support package, testbench, and C or assembly test programs that are specific to this small two-stage core, while reusing common agents and infrastructure from core-v-verif. Engineers working on CVE2 should use this repository for target-specific tests and use the shared CORE-V-VERIF guide for initial tool and environment setup.

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